-
+ 2E1120E28077B4FC31BC2DE704CBA9591DAAD2E4193737CF911A0DD49D4731843CC9FB9C3595F65C9E1BDF6A13D2D41011552DE688CFF10A7074ACE6827CC37Ffg.ucf(0 . 0)(1 . 47)
5 ///////////////////////////////////////////////////////////////////////////
6 // FUCKGOATS CPLD UCF constraint file. V.3K (December 2016.)
7 //
8 // This was written for an XC9572XL. It SHOULD work on any gate array of
9 // equal or greater size, but no such assurance is given.
10 // It SHOULD also work quite well in the form of an ASIC, or in TTL, or
11 // using any other reasonably-fast logic element.
12 //
13 // (C) 2016 No Such lAbs.
14 //
15 // You do not have, nor can you ever acquire the right to use, copy or
16 // distribute this software ; Should you use this software for any purpose,
17 // or copy and distribute it to anyone or in any manner, you are breaking
18 // the laws of whatever soi-disant jurisdiction, and you promise to
19 // continue doing so for the indefinite future. In any case, please
20 // always : read and understand any software ; verify any PGP signatures
21 // that you use - for any purpose.
22 ///////////////////////////////////////////////////////////////////////////
23
24 // Device : XC9572XL-5-VQ44
25 //
26 // --------------------------------
27 // /44 43 42 41 40 39 38 37 36 35 34 \
28 // | 1 33 |
29 // | 2 32 |
30 // | 3 31 |
31 // | 4 30 |
32 // | 5 XC9572XL-5-VQ44 29 |
33 // | 6 28 |
34 // | 7 27 |
35 // | 8 26 |
36 // | 9 25 |
37 // | 10 24 |
38 // | 11 23 |
39 // \ 12 13 14 15 16 17 18 19 20 21 22 /
40 // --------------------------------
41
42 NET "xtal" LOC = "P1"; // on-board 14.7456MHz resonator
43 NET "clk" LOC = "P33"; // master/slave clk ('RESET' on v1 pcb)
44
45 NET "IN_A" LOC = "P37"; // bottom analogue RNG connector
46 NET "IN_B" LOC = "P18"; // top analogue RNG connector
47
48 NET "ser_tx" LOC = "P28"; // serial out
49 NET "SAD" LOC = "P34"; // red lamp
50
51 ///////////////////////////////////////////////////////////////////////////