fg-genesis 1 ///////////////////////////////////////////////////////////////////////////
fg-genesis 2 // FUCKGOATS CPLD UCF constraint file. V.3K (December 2016.)
fg-genesis 3 //
fg-genesis 4 // This was written for an XC9572XL. It SHOULD work on any gate array of
fg-genesis 5 // equal or greater size, but no such assurance is given.
fg-genesis 6 // It SHOULD also work quite well in the form of an ASIC, or in TTL, or
fg-genesis 7 // using any other reasonably-fast logic element.
fg-genesis 8 //
fg-genesis 9 // (C) 2016 No Such lAbs.
fg-genesis 10 //
fg-genesis 11 // You do not have, nor can you ever acquire the right to use, copy or
fg-genesis 12 // distribute this software ; Should you use this software for any purpose,
fg-genesis 13 // or copy and distribute it to anyone or in any manner, you are breaking
fg-genesis 14 // the laws of whatever soi-disant jurisdiction, and you promise to
fg-genesis 15 // continue doing so for the indefinite future. In any case, please
fg-genesis 16 // always : read and understand any software ; verify any PGP signatures
fg-genesis 17 // that you use - for any purpose.
fg-genesis 18 ///////////////////////////////////////////////////////////////////////////
fg-genesis 19
fg-genesis 20 // Device : XC9572XL-5-VQ44
fg-genesis 21 //
fg-genesis 22 // --------------------------------
fg-genesis 23 // /44 43 42 41 40 39 38 37 36 35 34 \
fg-genesis 24 // | 1 33 |
fg-genesis 25 // | 2 32 |
fg-genesis 26 // | 3 31 |
fg-genesis 27 // | 4 30 |
fg-genesis 28 // | 5 XC9572XL-5-VQ44 29 |
fg-genesis 29 // | 6 28 |
fg-genesis 30 // | 7 27 |
fg-genesis 31 // | 8 26 |
fg-genesis 32 // | 9 25 |
fg-genesis 33 // | 10 24 |
fg-genesis 34 // | 11 23 |
fg-genesis 35 // \ 12 13 14 15 16 17 18 19 20 21 22 /
fg-genesis 36 // --------------------------------
fg-genesis 37
fg-genesis 38 NET "xtal" LOC = "P1"; // on-board 14.7456MHz resonator
fg-genesis 39 NET "clk" LOC = "P33"; // master/slave clk ('RESET' on v1 pcb)
fg-genesis 40
fg-genesis 41 NET "IN_A" LOC = "P37"; // bottom analogue RNG connector
fg-genesis 42 NET "IN_B" LOC = "P18"; // top analogue RNG connector
fg-genesis 43
fg-genesis 44 NET "ser_tx" LOC = "P28"; // serial out
fg-genesis 45 NET "SAD" LOC = "P34"; // red lamp
fg-genesis 46
fg-genesis 47 ///////////////////////////////////////////////////////////////////////////