(92 . 6)(92 . 25)
_m_tlbwr:
        ; no fields
        mov     ecx,   Sr(CP0_Wired)      ; ecx := CP0_Wired
%ifdef TLBWR_CHEAT ; 'Cheat' behaviour (see knobs.asm for rationale) :
        mov     AUX,   ecx                ; save this index in AUX, we will use
        mov     edx,   TLB_ENTRIES_COUNT - 1 ; index of last entry
        ; Move all TLB entries after the Wired entries down by one slot:
.tlbwr_slide: ; Start by replacing the last entry with the next-to-last:
        cmp     edx, AUX                  ; time to stop?
        je      .tlbr_slide_done          ; ... then stop.
        mov     ecx,   edx                ; ecx := edx
        dec     ecx                       ; ecx := ecx - 1 (prev. TLB index)
        mov     eax,   TLB_E(ecx)         ; eax := current TLB entry
        mov     TLB_E(edx), eax           ; move the current into the next
        mov     eax,   TLB_PFN_E(ecx)     ; eax := current PFN_EVEN entry
        mov     TLB_PFN_E(edx), eax       ; move the current into the next
        mov     eax,   TLB_PFN_O(ecx)     ; eax := current PFN_ODD entry
        mov     TLB_PFN_O(edx), eax       ; move the current into the next
        dec     edx                       ; move back by one
        jmp     .tlbwr_slide              ; Continue the slide.
.tlbr_slide_done: ; Now we freed up the top-most non-wired slot in TLB table:
%else ; 'Traditional' behaviour per the MIPS Standard:
        mov     ebx,   TLB_ENTRIES_COUNT  ; ebx := #tlbentries
        sub     ebx,   ecx                ; ebx := #tlbentries - Wired
        mov     edx,   0                  ; edx (upper half of dividend) := 0
(99 . 7)(118 . 8)
        div     ebx                       ; edx:eax / ebx
        add     edx,   ecx                ; edx (remainder) := edx + wired
        mov     AUX,   edx                ; make edx the index for tlb write
        call    _write_tlb_entry          ; Write the indexed TLB entry.
%endif
        call    _write_tlb_entry          ; Write the AUX-indexed TLB entry.
        jmp     _end_cycle
;-----------------------------------------------------------------------------

(446 . 7)(466 . 12)
        test    ecx,   ecx              ; Sel != 0 ?
        jnz     _mtc0_unknown           ; ... then unknown; else:
        and     ebx,   ~0x1F00          ; T           := T & ~0x1F00
        mov     Sr(CP0_EntryHi), ebx    ; CP0_EntryHi := T
        cmp     ebx, Sr(CP0_EntryHi)    ; Find whether changing CP0_EntryHi
        je      .Not_Changed_EntryHi    ; ... if not, skip;
.Changed_EntryHi:                       ; If we are changing CP0_EntryHi:
        Invalidate_TLB_Cache            ; Invalidate both R and W TLB Caches
        mov     Sr(CP0_EntryHi), ebx    ; CP0_EntryHi := ebx
.Not_Changed_EntryHi:
        jmp     _end_cycle              ; Done
;-----------------------------------------------------------------------------
_mtc0_r11: ;  0x0b