- FD686B4ADBDB138A08F6B8F95620FD0533B2BD68C5B5056D24100F28B552CB6E7AF74B32BFD739F029E065D257F456024D223073DA3F0F8168E6D98F75BE053D+ 2AC1B0ACACD2CD01845DC0E9AD36BAE84577B76ACE6BE6E079C7E11B96A22508301B7B0012B119164EC5C87AB196D180DA0A4E787D3B7AB9E3ED3436D82BEEA0m/mips_exc.asm(37 . 49)(37 . 31)
145 %endmacro
146 ;-----------------------------------------------------------------------------
147
148 ;------------------------------
149 ; Exception (and IRQ) Handler |
150 ;-----------------------------------------------------------------------------
151 _Handle_Exception:
152 ; Exception Prologue
153 ;-----------------------------------------------------------------------------
154 %macro EXC_HANDLER_PROLOGUE 0
155 Flg_Off InDelaySlot ; Clear the InDelaySlot Flag
156 bt CP0_Status, CP0St_EXL ; CF := EXL
157 jc _H_Exc_Off_Is_180 ; If EXL is 1, Offset := 0x180; else:
158 jc _H_Exc_Off_Is_180 ; If EXL is 1, Offset := 0x180; else:
159 ;; EXL is 0:
160 mov Sr(CP0_Epc), PC ; CP0_Epc := PC
161 Flg_Get RunningDelaySlot ; Are we running the delay slot?
162 jnc _H_Exc_Not_R_Delay ; If yes, then skip, else:
163 _H_Exc_R_Delay: ; We ARE running the delay slot:
164 jnc %%no_delay ; If yes, then skip, else:
165 %%yes_delay: ; We ARE running the delay slot:
166 sub Sr(CP0_Epc), 0x4 ; CP0_Epc := CP0_Epc - 0x4
167 bts CP0_Cause, CP0Cau_BD ; Set BD Flag in CP0_Cause
168 jmp _H_Exc_Test_TLB ; Proceed to test for TLBism
169 _H_Exc_Not_R_Delay: ; We are NOT running the delay slot:
170 jmp %%exc_prologue_done ; Continue in _Handle_Exception
171 %%no_delay: ; We are NOT running the delay slot:
172 btr CP0_Cause, CP0Cau_BD ; Clear BD Flag in CP0_Cause
173 _H_Exc_Test_TLB:
174 ;; Test whether this was a TLB Exception:
175 GetEXC eax ; EAX := the current exception code
176 cmp eax, EXC_TLBL ; was it EXC_TLBL ?
177 je __H_Exc_Was_TLB ; ... if yes, go to H_Exc_Was_TLB
178 cmp eax, EXC_TLBS ; was it EXC_TLBS ?
179 je __H_Exc_Was_TLB ; ... if yes, go to H_Exc_Was_TLB
180 ;; This was NOT a TLB Exception:
181 cmp eax, EXC_Int ; was code EXC_Int ?
182 jne _H_Exc_Off_Is_180 ; if not, Offset := 0x180
183 bt CP0_Cause, CP0Cau_IV ; Was CP0_Cause bit 23 (IV) zero?
184 jnc _H_Exc_Off_Is_180 ; if was zero, Offset := 0x180
185 ;; If CP0_Cause bit 23 != 0: Offset := 0x200
186 mov eax, 0x200 ; Offset := 0x200
187 jmp _H_Exc_Have_Offset ; Go to H_Exc_Have_Offset
188 __H_Exc_Was_TLB: ; This WAS a TLB Exception:
189 Flg_Get ExcWasTLBNoMatch ; CF := 'TLB No Match'
190 ;; TODO: in 'cmips', this case was reversed? why?
191 ;; For now, we'll do likewise:
192 jnc _H_Exc_Off_Is_180 ; ... if 0, Offset := 0x180
193 ;; Else: Offset := 0x0
194 xor eax, eax ; Clear EAX (Offset := 0)
195 jmp _H_Exc_Have_Offset ; Finish up
196 _H_Exc_Off_Is_180: ; Offset := 0x180
197 mov eax, 0x180 ; Set the Offset
198 _H_Exc_Have_Offset: ; We finished calculating the Offset:
199 %%exc_prologue_done:
200 %endmacro
201 ;-----------------------------------------------------------------------------
202
203 ;-----------------------------------------------------------------------------
204 ; Exception Epilogue:
205 ;-----------------------------------------------------------------------------
206 _Exception_Epilogue:
207 bts CP0_Status, CP0St_EXL ; Set the EXL Flag
208 mov PC, eax ; PC := Offset (eax)
209 mov eax, 0x80000000 ; Base that will be used if BEV=0
(90 . 3)(72 . 34)
211 ;; Done handling exception
212 jmp _cycle ; Start next cycle.
213 ;-----------------------------------------------------------------------------
214
215 ;------------------------------------------
216 ; Exception Handler: TLB NoMatch Fastpath |
217 ;-----------------------------------------------------------------------------
218 _Handle_Exception_TLB_NoMatch:
219 EXC_HANDLER_PROLOGUE
220 xor eax, eax ; Clear EAX (Offset := 0)
221 jmp _Exception_Epilogue ; Finish up
222 ;-----------------------------------------------------------------------------
223
224 ;-------------------------------------------------------
225 ; Exception Handler: Not-IRQ, Not-TLB-NoMatch Fastpath |
226 ;-----------------------------------------------------------------------------
227 _Handle_Exception_Other:
228 EXC_HANDLER_PROLOGUE
229 _H_Exc_Off_Is_180:
230 mov eax, 0x180 ; Set the Offset
231 jmp _Exception_Epilogue ; Finish up
232 ;-----------------------------------------------------------------------------
233
234 ;----------------------------------
235 ; Exception Handler: IRQ Fastpath |
236 ;-----------------------------------------------------------------------------
237 _Handle_Exception_IRQ:
238 EXC_HANDLER_PROLOGUE
239 bt CP0_Cause, CP0Cau_IV ; Was CP0_Cause bit 23 (IV) zero?
240 jnc _H_Exc_Off_Is_180 ; if was zero, Offset := 0x180
241 ;; If CP0_Cause bit 23 != 0: Offset := 0x200
242 mov eax, 0x200 ; Offset := 0x200
243 jmp _Exception_Epilogue ; Finish up
244 ;-----------------------------------------------------------------------------