(23 . 6)(23 . 21)
93 ;-----------------------------------------------------------------------------
94
95 ;-----------------------------------------------------------------------------
96 ; If TLBWR_CHEAT is enabled, the TLBWR ('Write Random TLB Entry') instruction
97 ; will slide all unwired entries down by one slot and write into the freed
98 ; slot near the top permitted by CP0_Wired, instead of the traditional
99 ; behaviour (where entry indexed by a modulus of the tick counter is killed.)
100 ; No known code (incl. Linux) tries to rely on the absolute position of
101 ; unwired TLB entries after a TLBWR instruction. So this gives faster lookup
102 ; when iterating over TLB, as the newer unwired entries will aggregate near
103 ; the base of the table. Iron MIPSen do not iterate, they look up in parallel,
104 ; ergo the original MIPS designer did not see any reason to attempt to order
105 ; TLB entries by frequency of use.
106 ;-----------------------------------------------------------------------------
107 %define TLBWR_CHEAT 1
108 ;-----------------------------------------------------------------------------
109
110 ;-----------------------------------------------------------------------------
111 ; Alignment Grain
112 ;-----------------------------------------------------------------------------
113 %define GRAIN 32