(23 . 21)(23 . 6)
125 ;-----------------------------------------------------------------------------
126
127 ;-----------------------------------------------------------------------------
128 ; If TLBWR_CHEAT is enabled, the TLBWR ('Write Random TLB Entry') instruction
129 ; will slide all unwired entries down by one slot and write into the freed
130 ; slot near the top permitted by CP0_Wired, instead of the traditional
131 ; behaviour (where entry indexed by a modulus of the tick counter is killed.)
132 ; No known code (incl. Linux) tries to rely on the absolute position of
133 ; unwired TLB entries after a TLBWR instruction. So this gives faster lookup
134 ; when iterating over TLB, as the newer unwired entries will aggregate near
135 ; the base of the table. Iron MIPSen do not iterate, they look up in parallel,
136 ; ergo the original MIPS designer did not see any reason to attempt to order
137 ; TLB entries by frequency of use.
138 ;-----------------------------------------------------------------------------
139 %define TLBWR_CHEAT 1
140 ;-----------------------------------------------------------------------------
141
142 ;-----------------------------------------------------------------------------
143 ; Alignment Grain
144 ;-----------------------------------------------------------------------------
145 %define GRAIN 32