- 1427E0C04C15C733AED037B1A56252C2F7F8EE7960171AB548B6CE1244320EA1E9B4AA00045D94A4478AAD0E605E9206AA9E8B92581BE252B3E08C893ED372FE+ 1A9CF2B89DFF48898ABB798D358E65AE567CDB25CA0521F248D4BB1CB388C604F6D9E17B61B25F6F1822AE4304DB1EE0059DB15B2C36858ACA08EC46653CC0A4m/cpustate.asm(18 . 7)(18 . 7)
13
14 ;-----------------------------------------------------------------------------
15 ; MIPS Processor State.
16 ; Note: PC, nPC, CP0_Status, CP0_Cause, CP0_Compare, are housed in x86 regs.
17 ; Note: PC, nPC, CP0_Status, CP0_Cause, are housed in x86 regs.
18 struc MCPU
19 .Regs resd 32 ; The standard MIPS Register Set
20 .LO resd 1 ; Multiplication/division results - Low Half
(33 . 20)(33 . 16)
22 .CP0_BadVAddr resd 1 ; Addr. of most recent addr.-caused exception
23 .CP0_ErrorEpc resd 1 ; Program counter at last exception
24 .CP0_PageMask resd 1 ; Control variable page sizes in TLB entries
25 ;; The TLB:
26 .TLB_Entries resd TLB_ENTRIES_COUNT ; TLB entries (without PFN)
27 .TLB_PFN_Even resd TLB_ENTRIES_COUNT ; TLB PFN0
28 .TLB_PFN_Odd resd TLB_ENTRIES_COUNT ; TLB PFN1
29 .CP0_Compare resd 1 ; Timer interrupt control
30 .TLB_PFN resq TLB_ENTRIES_COUNT ; TLB PFN : |ODD|EVEN|
31 endstruc
32 ;-----------------------------------------------------------------------------
33
34 ;-----------------------------------------------------------------------------
35 ; Refer to the N-th TLB Entry:
36 ;-----------------------------------------------------------------------------
37 %define TLB_E(N) dword [M_Base_32 + MCPU.TLB_Entries + 4 * (N)]
38 ; N-th PFN :
39 %define TLB_PFN_E(N) dword [M_Base_32 + MCPU.TLB_PFN_Even + 4 * (N)]
40 %define TLB_PFN_O(N) dword [M_Base_32 + MCPU.TLB_PFN_Odd + 4 * (N)]
41 %define TLB_PFN(N) qword [M_Base_64 + MCPU.TLB_PFN + 8 * (N)]
42 ;-----------------------------------------------------------------------------
43
44 ;-----------------------------------------------------------------------------
(61 . 7)(57 . 7)
46 ; TODO: is it possible to use the upper halves of the 64bit regs for anything?
47 ; ... or entirely worthless from intel's idiocy of 'auto-zero on mov' ?
48 ;-----------------------------------------------------------------------------
49 %define Flag_Reg edi ; Delay, Exception, etc flags
50 %define Flag_Reg edi ; Delay, Exception, etc flags and TLB G
51 %define RAM_Floor rsi ; Physical (x86) address of 1st RAM word
52 %define RAM_Ceiling r8 ; Physical (x86) address of last RAM word
53 %define PC r9d ; Current Program Counter
(69 . 23)(65 . 26)
55 %define CP0_Status r11d ; Processor status and control
56 %define CP0_Cause r12d ; Cause of last general exception
57 %define CP0_Count r13d ; Processor cycle count
58 %define CP0_Compare r14d ; Timer interrupt control
59 %define TLB_Flags r14 ; TLB D1/V1/D0/V0 Flags
60 %define AUX r15d ; Additional TMP for certain ops
61 %define AUX64 r15 ; all 64bits of AUX
62
63 ; TODO: 'Suspend to RAM' routine for all of the above.
64 ;-----------------------------------------------------------------------------
65
66 ;-----------------------------------------------------------------------------
67 ; XMM Regs used for TLB Caching:
68 ; XMM Regs:
69 ;-----------------------------------------------------------------------------
70 %define Rd_E_Last_Tag xmm5 ; Last good Tag on reading Even vAddr
71 %define Rd_E_Last_PFN xmm6 ; Last good PFN on reading Even vAddr
72 %define Rd_O_Last_Tag xmm7 ; Last good Tag on reading Odd vAddr
73 %define Rd_O_Last_PFN xmm8 ; Last good PFN on reading Odd vAddr
74 %define Wr_E_Last_Tag xmm9 ; Last good Tag on writing Even vAddr
75 %define Wr_E_Last_PFN xmm10 ; Last good PFN on writing Even vAddr
76 %define Wr_O_Last_Tag xmm11 ; Last good Tag on writing Odd vAddr
77 %define Wr_O_Last_PFN xmm12 ; Last good PFN on writing Odd vAddr
78 ;; 16 Tags:
79 %define TLB_TAG_BYTE_0 xmm5 ; Byte 0 of Tag
80 %define TLB_TAG_BYTE_1 xmm6 ; Byte 1 of Tag
81 %define TLB_TAG_BYTE_2 xmm7 ; Byte 2 of Tag
82 %define XMM_T0 xmm8 ; Temp
83
84 %define R_TLB_Last_Good_Tag xmm9 ; Last good Tag on reading vAddr (|O|E|)
85 %define W_TLB_Last_Good_Tag xmm10 ; Last good Tag on writing vAddr (|O|E|)
86 %define R_TLB_Last_Good_PFN xmm11 ; Last good PFN on reading vAddr (|O|E|)
87 %define W_TLB_Last_Good_PFN xmm12 ; Last good PFN on writing vAddr (|O|E|)
88 ;-----------------------------------------------------------------------------
89
90 ;-----------------------------------------------------------------------------
(128 . 8)(127 . 8)
92 mov nPC, eax
93 mov CP0_Status, eax
94 mov CP0_Cause, eax
95 mov CP0_Count, eax
96 mov CP0_Compare, eax
97 mov CP0_Count, eax
98 xor TLB_Flags, TLB_Flags
99 ;; Init 'slow' MIPS Regs:
100 mov ecx, 0
101 _init_reg:
(149 . 6)(148 . 7)
103 mov Sr(CP0_Epc), eax
104 mov Sr(CP0_BadVAddr), eax
105 mov Sr(CP0_ErrorEpc), eax
106 mov Sr(CP0_Compare), eax
107 Flg_Clear_All ; Reset all misc Flags to 0
108 bts CP0_Status, CP0St_ERL ; Start in kernel mode w/ unmapped useg
109 ret