-
+ F82EA8FEBCEB149C589262C1387C2A99D641219DAC217DE1BA1E3E99ED8B815B5FE4F6B68128CB55FEFED5BD41B4D764C802B6EBCE34BD4580769027CA001CD7
m/mips.asm

(0 . 0)(1 . 117)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                          ;;
;; This file is part of 'M', a MIPS system emulator.                        ;;
;;                                                                          ;;
;; (C) 2019 Stanislav Datskovskiy ( www.loper-os.org )                      ;;
;; http://wot.deedbot.org/17215D118B7239507FAFED98B98228A001ABFFC7.html     ;;
;;                                                                          ;;
;; You do not have, nor can you ever acquire the right to use, copy or      ;;
;; distribute this software ; Should you use this software for any purpose, ;;
;; or copy and distribute it to anyone or in any manner, you are breaking   ;;
;; the laws of whatever soi-disant jurisdiction, and you promise to         ;;
;; continue doing so for the indefinite future. In any case, please         ;;
;; always : read and understand any software ; verify any PGP signatures    ;;
;; that you use - for any purpose.                                          ;;
;;                                                                          ;;
;; See also http://trilema.com/2015/a-new-software-licensing-paradigm .     ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;-----------------------------------------------------------------------------
; Value of Program Counter (PC) on Warmup
;-----------------------------------------------------------------------------
%define INIT_PC       0xBFC00000 ; Per traditional MIPS standard.
;-----------------------------------------------------------------------------

;-----------------------------------------------------------------------------
; # of TLB entries. Could have more; but would have to change not only here.
;-----------------------------------------------------------------------------
%define TLB_ENTRIES_COUNT     16 ; in principle could have more.
;-----------------------------------------------------------------------------

;-----------------------------------------------------------------------------
; MIPS Exceptions Codes (See CP0_Cause Flags re: where they sit)
;-----------------------------------------------------------------------------
%define EXC_Int      0 ; Interrupt
%define EXC_Mod      1 ; TLB modification exception
%define EXC_TLBL     2 ; TLB exception (load or instruction fetch)
%define EXC_TLBS     3 ; TLB exception (store)
%define EXC_AdEL     4 ; Address error exception (load or instruction fetch)
%define EXC_AdES     5 ; Address error exception (store)
%define EXC_IBE      6 ; Bus error exception (instruction fetch)
%define EXC_DBE      7 ; Bus error exception (data reference: load or store)
%define EXC_SYS      8 ; Syscall exception
%define EXC_BP       9 ; Breakpoint exception
%define EXC_RI      10 ; Reserved instruction exception
%define EXC_CpU     11 ; Coprocessor Unusable exception
%define EXC_Ov      12 ; Arithmetic Overflow exception
%define EXC_Tr      13 ; Trap exception
%define EXC_Watch   23 ; Reference to WatchHi/WatchLo address
%define EXC_MCheck  24 ; Machine check
;-----------------------------------------------------------------------------

;-----------------------------------------------------------------------------
; MIPS CP0_Cause Register
;-----------------------------------------------------------------------------
; 11111111111111110000000000000000  EEEEE - Exception Code; IIIIIIII - IRQ;
; FEDCBA9876543210FEDCBA9876543210  IV - Indicates whether an interrupt
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~       exception uses the general exception
; B0CC0000IW000000IIIIIIII0EEEEE00       vector or a special interrupt vector:
; D EE    VP      76543210               0: General exception vector (0x180)
;                                        1: Special interrupt vector (0x200)
; BD - Indicates whether last exception taken occurred in a branch delay slot.
;      0: Not in delay slot; 1: In delay slot.
;      BD bit is not updated on a new exception if the EXL bit is set.
; IRQ0, IRQ1 -- 'software IRQ'; IRQ2..IRQ7 -- iron IRQ.
; MIPS Timer (powered by CP0_Count and CP0_Compare) is perma-soldered to IRQ7.
;-----------------------------------------------------------------------------
%define CP0Cau_IRQ_Bottom   8 ; Index of bit in CP0_Cause where IRQ # lives
%define CP0Cau_IV          23 ; Whether exception uses general or special vect
%define CP0Cau_BD          31 ; Whether exception occurred in branch delay slt
;-----------------------------------------------------------------------------

;-----------------------------------------------------------------------------
; MIPS CP0_Status Register
;-----------------------------------------------------------------------------
%define CP0St_CU3      31 ; Coprocessor Access CU3 (unused)
%define CP0St_CU2      30 ; Coprocessor Access CU2 (unused)
%define CP0St_CU1      29 ; Coprocessor Access CU1 (unused)
%define CP0St_CU0      28 ; Coprocessor Access CU0 (unused)
%define CP0St_RP       27 ; Reduced Power Mode (unused)
%define CP0St_FR       26 ; Floating Point Reg Mode -- Unused on 32-bit MIPS
%define CP0St_RE       25 ; Reverse-Endianism (0: user, 1: flipped) - unused
%define CP0St_MX       24 ; Unused on 32-bit MIPS
%define CP0St_PX       23 ; Unused on 32-bit MIPS
%define CP0St_BEV      22 ; BEV (0: Normal Exception Vector, 1: Bootstrap)
%define CP0St_TS       21 ; TLB 'multi-match' shutdown (unused)
%define CP0St_SR       20 ; Soft Reset (0: not soft, 1: soft)
%define CP0St_NMI      19 ; NMI (unused)
%define CP0St_IM        8 ; Start of Interrupt Mask (0: IRQ OFF, 1: IRQ ON)
%define CP0St_KX        7 ; Unused on 32-bit MIPS
%define CP0St_SX        6 ; Unused on 32-bit MIPS
%define CP0St_UX        5 ; Unused on 32-bit MIPS
%define CP0St_UM        4 ; User Mode (0: Kernel Mode, 1: User Mode)
%define CP0St_KSU       3 ; Unused
%define CP0St_ERL       2 ; Error Level (0: Normal, 1: Error)
%define CP0St_EXL       1 ; Exception Level (0: Normal, 1: Kernel)
%define CP0St_IE        0 ; Interrupt Enable
;-----------------------------------------------------------------------------

;-----------------------------------------------------------------------------
; MIPS TLB Entry.
; We don't use C0 and C1 anywhere! and so we can put all of it in 32bits:
;-----------------------------------------------------------------------------
; 11111111111111110000000000000000
; FEDCBA9876543210FEDCBA9876543210
; --------------------------------
; GVVDDAAAAAAAAVVVVVVVVVVVVVVVVVVV
; |1010| ASID ||      VPN2       |
;-----------------------------------------------------------------------------
%define TLB_VPN2_Mask    0x7FFFF ; 19 bits
%define TLB_ASID_Mask       0xFF ; 8 bits
%define TLB_ASID_Shift        19 ; sits after VPN2 Mask
%define TLB_D0                27 ; 27th bit
%define TLB_D1                28 ; 28th bit
%define TLB_V0                29 ; 29th bit
%define TLB_V1                30 ; 30th bit
%define TLB_G                 31 ; 31st bit (last)
;-----------------------------------------------------------------------------