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+ 6CEECB9422F3D01B04ED2ECB183FB96665FF969087E2967ECCEF2703337401AFB4F0EC91E4B7EFDA625AE4534BA1C3DABA539A1FC794B2E594D7404DDF72399Cm/cpustate.asm(0 . 0)(1 . 142)
239 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
240 ;; ;;
241 ;; This file is part of 'M', a MIPS system emulator. ;;
242 ;; ;;
243 ;; (C) 2019 Stanislav Datskovskiy ( www.loper-os.org ) ;;
244 ;; http://wot.deedbot.org/17215D118B7239507FAFED98B98228A001ABFFC7.html ;;
245 ;; ;;
246 ;; You do not have, nor can you ever acquire the right to use, copy or ;;
247 ;; distribute this software ; Should you use this software for any purpose, ;;
248 ;; or copy and distribute it to anyone or in any manner, you are breaking ;;
249 ;; the laws of whatever soi-disant jurisdiction, and you promise to ;;
250 ;; continue doing so for the indefinite future. In any case, please ;;
251 ;; always : read and understand any software ; verify any PGP signatures ;;
252 ;; that you use - for any purpose. ;;
253 ;; ;;
254 ;; See also http://trilema.com/2015/a-new-software-licensing-paradigm . ;;
255 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
256
257 ;-----------------------------------------------------------------------------
258 ; MIPS Processor State.
259 ; Note: PC, nPC, CP0_Status, CP0_Cause, CP0_Compare, are housed in x86 regs.
260 struc MCPU
261 .Regs resd 32 ; The standard MIPS Register Set
262 .LO resd 1 ; Multiplication/division results - Low Half
263 .HI resd 1 ; Multiplication/division results - High Half
264 .CP0_Index resd 1 ; Index into the TLB array
265 .CP0_EntryHi resd 1 ; High-order portion of the TLB entry
266 .CP0_EntryLo0 resd 1 ; Low portion of TLB entry for even-#'d pages
267 .CP0_EntryLo1 resd 1 ; Low portion of TLB entry for odd-#'d pages
268 .CP0_Context resd 1
269 .CP0_Wired resd 1 ; The number of fixed ('wired') TLB entries
270 .CP0_Epc resd 1 ; Exception program counter return address
271 .CP0_BadVAddr resd 1 ; Addr. of most recent addr.-caused exception
272 .CP0_ErrorEpc resd 1 ; Program counter at last exception
273 .CP0_PageMask resd 1 ; Control variable page sizes in TLB entries
274 ;; The TLB:
275 .TLB_Entries resd TLB_ENTRIES_COUNT ; TLB entries (without PFN)
276 .TLB_PFN_Even resd TLB_ENTRIES_COUNT ; TLB PFN0
277 .TLB_PFN_Odd resd TLB_ENTRIES_COUNT ; TLB PFN1
278 endstruc
279 ;-----------------------------------------------------------------------------
280
281 ;-----------------------------------------------------------------------------
282 ; Refer to the N-th TLB Entry:
283 ;-----------------------------------------------------------------------------
284 %define TLB_E(N) dword [M_Base_32 + MCPU.TLB_Entries + 4 * (N)]
285 ; N-th PFN :
286 %define TLB_PFN_E(N) dword [M_Base_32 + MCPU.TLB_PFN_Even + 4 * (N)]
287 %define TLB_PFN_O(N) dword [M_Base_32 + MCPU.TLB_PFN_Odd + 4 * (N)]
288 ;-----------------------------------------------------------------------------
289
290 ;-----------------------------------------------------------------------------
291 section .bss
292 align GRAIN ; MIPS CPU State
293 MIPS_State resb MCPU_size
294 section .text
295 ;-----------------------------------------------------------------------------
296
297 ;-----------------------------------------------------------------------------
298 ; Global 'fast' MIPS State:
299 ; TODO: is it possible to use the upper halves of the 64bit regs for anything?
300 ; ... or entirely worthless from intel's idiocy of 'auto-zero on mov' ?
301 ;-----------------------------------------------------------------------------
302 %define Flag_Reg edi ; Delay, Exception, etc flags
303 %define RAM_Floor rsi ; Physical (x86) address of 1st RAM word
304 %define RAM_Ceiling r8 ; Physical (x86) address of last RAM word
305 %define PC r9d ; Current Program Counter
306 %define nPC r10d ; 'Next' Program Counter
307 %define CP0_Status r11d ; Processor status and control
308 %define CP0_Cause r12d ; Cause of last general exception
309 %define CP0_Count r13d ; Processor cycle count
310 %define CP0_Compare r14d ; Timer interrupt control
311 %define AUX r15d ; Additional TMP for certain ops
312
313 ; TODO: 'Suspend to RAM' routine for all of the above.
314 ;-----------------------------------------------------------------------------
315
316 ;-----------------------------------------------------------------------------
317 ; Access to MIPS Registers that live in MCPU (Emulator State) :
318 ;-----------------------------------------------------------------------------
319 ; Refer to given MIPS special Reg:
320 ;-----------------------------------------------------------------------------
321 %define Sr(N) dword [M_Base_32 + MCPU. %+ N]
322 ;-----------------------------------------------------------------------------
323 ; Refer to Nth Reg:
324 ;-----------------------------------------------------------------------------
325 %define R(N) Sr(Regs + 4 * (N))
326 ;-----------------------------------------------------------------------------
327
328 ;-----------------------------------------------------------------------------
329 ; Update given MIPS Reg # with new value, but always avoid overwriting R(0)
330 ;-----------------------------------------------------------------------------
331 ; TODO: measure if this is actually faster than simply R(31) := 0 every time
332 %macro Wr_Reg 2 ; params: %1: Reg # %2: PC reg with new value
333 xor AUX, AUX ; Clear AUX
334 test %1, %1 ; Set Z if destination reg # is R(0)
335 cmovz %2, AUX ; If Z: Replace written value with zero
336 mov R(%1), %2 ; Regs[rD] := new value
337 ;;;; alt variant:
338 ; mov R(%1), %2 ; Regs[rD] := new value
339 ; mov R(0), 0
340 ;;;; TODO: which is actually faster ?
341 %endmacro
342 ;-----------------------------------------------------------------------------
343
344 ;-----------------------------------------------------------------------------
345 ; Init MIPS CPU:
346 ;-----------------------------------------------------------------------------
347 _cpu_reset:
348 xor eax, eax ; eax := 0
349 mov AUX, eax ; Clear AUX register
350 mov M_Base_64, MIPS_State ; Set RBP to point to MIPS CPU State
351 ;; Init 'fast' MIPS Regs:
352 mov PC, INIT_PC
353 mov nPC, eax
354 mov CP0_Status, eax
355 mov CP0_Cause, eax
356 mov CP0_Count, eax
357 mov CP0_Compare, eax
358 ;; Init 'slow' MIPS Regs:
359 mov ecx, 0
360 _init_reg:
361 mov R(ecx), eax
362 inc ecx
363 cmp ecx, 32
364 jb _init_reg
365 xor ecx, ecx
366 mov Sr(HI), eax
367 mov Sr(LO), eax
368 mov Sr(CP0_Index), eax
369 mov Sr(CP0_EntryHi), eax
370 mov Sr(CP0_EntryLo0), eax
371 mov Sr(CP0_EntryLo1), eax
372 mov Sr(CP0_Context), eax
373 mov Sr(CP0_Wired), eax
374 mov Sr(CP0_Epc), eax
375 mov Sr(CP0_BadVAddr), eax
376 mov Sr(CP0_ErrorEpc), eax
377 Flg_Clear_All ; Reset all misc Flags to 0
378 bts CP0_Status, CP0St_ERL ; Start in kernel mode w/ unmapped useg
379 ret
380 ;-----------------------------------------------------------------------------