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+ F6312358148D7EBEDDDCE03178DB0943D7A753219ECBE0B803407F99A02173E629EF6E8AA9C0F936BA05322461DAE2003E81BEB9A37A3E74F8253C883ACEF43CMakefile(0 . 0)(1 . 94)
497 ###########################################################################
498 ## FUCKGOATS CPLD Makefile. V.3K (December 2016.)
499 ##
500 ## This was written for an XC9572XL. It SHOULD work on any gate array of
501 ## equal or greater size, but no such assurance is given.
502 ## It SHOULD also work quite well in the form of an ASIC, or in TTL, or
503 ## using any other reasonably-fast logic element.
504 ##
505 ## (C) 2016 No Such lAbs.
506 ##
507 ## You do not have, nor can you ever acquire the right to use, copy or
508 ## distribute this software ; Should you use this software for any purpose,
509 ## or copy and distribute it to anyone or in any manner, you are breaking
510 ## the laws of whatever soi-disant jurisdiction, and you promise to
511 ## continue doing so for the indefinite future. In any case, please
512 ## always : read and understand any software ; verify any PGP signatures
513 ## that you use - for any purpose.
514 ###########################################################################
515
516 ###########################################################################
517 ## make clean && make #<<<<<<<<<<<< build
518 ## make burn #<<<<<<<<<<<< burn ROM with Xilinx's burner
519 ###########################################################################
520
521 ## Project name
522 PROJECT=fg
523 ## Part number
524 PART=XC9572XL-5-vq44
525 ## Output configuration file
526 OUTPUT=$(PROJECT).jed
527 ## Verilog sources
528 SOURCES=fg.v
529 ## Constraints file
530 UCF=$(PROJECT).ucf
531
532 ## Path to Xilinx tools, blank if in $PATH, must end in /
533 ## YOU MUST CHANGE THIS TO YOURS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
534 XILINX=/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/
535 ## If you have some OTHER version of the Xilinx turdware, this build MAY work.
536
537 WD=work
538 PB=$(WD)/$(PROJECT)
539
540 XSTFLAGS=-opt_mode Speed -opt_level 2 -verilog2001 YES
541 CPLDFITFLAGS=-slew fast -power std -terminate keeper -unused float -optimize speed -init low
542
543 .PHONY: all clean
544
545 all: $(PB).tim $(OUTPUT)
546
547 $(WD):
548 mkdir $(WD)/
549
550 $(PB).ngc: $(SOURCES)
551 @[ ! -e $(WD) ] && mkdir $(WD) || true
552 @echo "Generating $(PB).prj..."
553 @rm -f $(PB).prj
554 @for i in $(SOURCES); do \
555 echo "verilog $(PROJECT) $$i" >> $(PB).prj; \
556 done
557 @echo "DEFAULT_SEARCH_ORDER" > $(PB).lso
558 @echo "set -tmpdir $(WD) -xsthdpdir $(WD)" > $(PB).xst
559 @echo "run -ifn $(PB).prj -ifmt mixed -top $(PROJECT) -ofn $@ -ofmt NGC -p $(PART) $(XSTFLAGS) -lso $(PB).lso" >> $(PB).xst
560 $(XILINX)xst -ifn $(PB).xst -ofn $(PB)_xst.log
561
562 $(PB).ngd: $(PB).ngc $(UCF)
563 cd $(WD) ; $(XILINX)ngdbuild -p $(PART) -uc ../$(UCF) ../$< ../$@
564
565 $(PB).vm6: $(PB).ngd
566 cd $(WD) ; $(XILINX)cpldfit -exhaust -p $(PART) ../$<
567
568 $(PB).tim: $(PB).vm6
569 cd $(WD) ; $(XILINX)taengine -l ../$@ -detail -f $(PROJECT) ../$<
570
571 $(PB).jed: $(PB).vm6
572 cd $(WD) ; $(XILINX)hprep6 -i ../$<
573 @echo "Generating $(PB).cmd..."
574 @echo "setmode -bscan" > $(PB).cmd
575 @echo "setcable -p auto" >> $(PB).cmd
576 @echo "Identify -inferir" >> $(PB).cmd
577 @echo "ReadIdcode -p 1" >> $(PB).cmd
578 @echo "assignFile -p 1 -file $(PROJECT).jed" >> $(PB).cmd
579 @echo "erase -p 1 -o" >> $(PB).cmd
580 @echo "program -p 1" >> $(PB).cmd
581 @echo "quit" >> $(PB).cmd
582
583 burn:
584 cd $(WD) ; $(XILINX)impact -batch $(PROJECT).cmd
585
586 %: $(WD)/%
587 @echo "Output $@ is ready"
588
589 clean:
590 rm -rf $(WD) $(OUTPUT) _xmsgs